The present trend in semiconductor technology is toward large scale integration of devices with very high speed and low power performance. The parameters that are essential to such high performance bipolar transistors include the presence of low parasitic capacitances as realized by shallow vertical junctions, and small horizontal geometries. In other words, it is necessary to make the devices in the integrated circuits as small as possible in both the horizontal and vertical directions.
With advances in semiconductor processing technology such as in the fields of ion implantation, dielectric isolation, electron beam and X-ray lithography and the like, fabrication of ultra high performance integrated circuit devices can be achieved. In other process technologies, fabrication of high performance integrated circuit devices has been improved.
One approach developed to reduce the size of integrated circuits has been the use of trench or slot isolation to isolate adjacent bipolar structures. Because this technique incorporates etching grooves into the semiconductor wafers adjacent to those regions in which PN junctions are to be formed, it becomes increasingly important to make the device as shallow possible in order to minimize the depth to which the groove must be etched.
The Texas Instruments process illustrated in FIG. 1 is typical of advanced bipolar processes as presently executed. As can be seen, it includes an outboard collector 10 which is isolated by field oxide 12 from the remainder of the device, thereby extending the horizontal region of the integrated circuit occupied by each NPN transistor. Similar efforts have been made by IBM as disclosed in U.S. Pat. Nos. 4,392,149 4,319,932 and 4,338,138. All of these patents are characterized by a resulting structure including a remote collector. They are also characterized by a relatively deep structure to incorporate the buried layer, which is necessary to get a low sheet resistance in the buried layer. This deep buried layer results in the need for providing a trench or slot or a deep isolation with the oxide isolation negative results discussed above.
Use of a separate collector also requires providing a separate island in the oxide to make connection to this collector. Use of a remote collector also requires provision of a relatively thick buried layer to provide the desired low resistance between emitter and collector. It should be noted that in prior art structures, to achieve a low sheet resistivity for the buried layer requires that the buried layer be about 3 microns thick. Formation of the buried layer further requires considerable heat cycling and heavy doping, all of which introduces stresses into the finished structure, and results in a relatively deep structure. Additionally, putting down the P-poly first requires that the area which is to become the active emitter be subjected to the etch processing required to open this P-poly for the N-poly emitter which comes later. This potentially subjects the single crystal silicon in the active emitter to etch damage which can induce emitter defects. Another difficulty that follows from the use of processes of the type appearing in FIG. 1 is that in order to obtain minimum a geometry structure, the emitter 14 is self-aligned with the active base 16. However, this requires that the P-poly layer 18 has to make contact to the active base 16 by diffusing the extrinsic base regions 20 under the oxide spacers 22 which separate the N-poly layer 24 and the P-poly layer 18. This requires significant heat treatment of the extrinsic base regions 20 and the intrinsic base regions and this extra heat treatment makes the intrinsic base regions 16 relatively deep. The provision of deep extrinsic base regions reduces the ability to obtain shallow junctions which is one of the objectives of this process design. Further, if the collector 10 were moved to be more closely adjacent to the base region, very high collector base capacitance, and relatively low breakdown voltages would result. Therefore, the processes disclosed in the prior art are relatively difficult to control in terms of achieving the process objectives of optimizing shallow junctions, minimum device area, low defects and low parasitic capacitances, with the highest performance possible.